STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

VI - MEMORY TIMING (continued)

VI.2 - Static Memories

Figure 33 : Static Memory Read Signals from the Multi-HDLC

NDS fro m µP

T

(or equivalent)

a

MAS TE R CLO C K

applied to XTAL1 P in

a

Tota l Rea d Cycle

ADM0/18

HZ

1/f

a

a

HZ

NCE 0 /7

NWE

NOE

HZ

DM0/15 from

S RAM Circuit

Note : S e e

MBL De finition

Twz

HZ

Ts Th

Each s igna l de livere d by the MHDLC

is high impeda nce outside this time

Symbol

T

1/f

a

Twz

Ts

Th

Parameter

Delay between Data Strobe delivered by the mP and beginning of

cycle

f: Masterclock frequency

Total read cycle: Twz + 1/f

Delay between Masterclock and Edge of each signal delivered by the

MHDLC (30pF)

NOE width

Set-up Time Data /NOE Rising Edge

Hold Time Data /NOE Rising Edge

Min.

2/f

1/f

20

0

Typ.

20

Max.

4/f

1/f

Unit

ns

ns

ns

ns

44/83

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