STLC5464 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5464 Datasheet PDF : 83 Pages
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STLC5464
VI - MEMORY TIMING (continued)
Figure 34 : Static Memory Write Signals from the Multi-HDLC
NDS from µP
T
(or equivalent)
a
MASTERCL OCK
applied to XTAL1 Pin
a
Total Write Cycle
a
1/f
a
a
ADM0/18
HZ
HZ
NCE0/7
Tuv
NWE
NOE
DM0/15
HZ
HZ
Note : See
Each signal delivered by the MHDLC
MBL Definition
is high impedance outside this time
Symbol
Parameter
Min. Typ. Max. Unit
T
Delay between Data Strobe delivered by the µP and beginning of
2/f
cycle
1/f f : Masterclock frequency
a
Delay between Masterclock and Edge of each signal delivered by the
20
ns
MHDLC (30pF)
Tuv NCE width
1/f
4/f
ns
Note : Total Write Cycle : Tuv + 1/f
45/83
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