DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—

15.6.24MMC Transmit 64 Octet Good Bad Frame Counter Register

(TX64OCTETS_GB)—Offset 124h ............................................................ 355

15.6.25MMC Transmit 65 to 127 Octet Good Bad Frame Counter Register

(TX65TO127OCTETS_GB)—Offset 128h ................................................... 355

15.6.26MMC Transmit 128 to 255 Octet Good Bad Frame Counter Register

(TX128TO255OCTETS_GB)—Offset 12Ch ................................................. 356

15.6.27MMC Transmit 256 to 511 Octet Good Bad Frame Counter Register

(TX256TO511OCTETS_GB)—Offset 130h.................................................. 356

15.6.28MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Register

(TX512TO1023OCTETS_GB)—Offset 134h ................................................ 356

15.6.29MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Register

(TX1024TOMAXOCTETS_GB)—Offset 138h ............................................... 357

15.6.30MMC Transmit Unicast Good Bad Frame Counter Register

(TXUNICASTFRAMES_GB)—Offset 13Ch ................................................... 357

15.6.31MMC Transmit Multicast Good Bad Frame Counter Register

(TXMULTICASTFRAMES_GB)—Offset 140h................................................ 358

15.6.32MMC Transmit Broadcast Good Bad Frame Counter Register

(TXBROADCASTFRAMES_GB)—Offset 144h .............................................. 358

15.6.33MMC Transmit Underflow Error Frame Counter Register

(TXUNDERFLOWERROR)—Offset 148h ..................................................... 359

15.6.34MMC Transmit Single Collision Good Frame Counter Register

(TXSINGLECOL_G)—Offset 14Ch............................................................. 359

15.6.35MMC Transmit Multiple Collision Good Frame Counter Register

(TXMULTICOL_G)—Offset 150h............................................................... 360

15.6.36MMC Transmit Deferred Frame Counter Register (TXDEFERRED)—Offset

154h ................................................................................................... 360

15.6.37MMC Transmit Late Collision Frame Counter Register (TXLATECOL)—Offset

158h ................................................................................................... 360

15.6.38MMC Transmit Excessive Collision Frame Counter Register

(TXEXESSCOL)—Offset 15Ch .................................................................. 361

15.6.39MMC Transmit Carrier Error Frame Counter Register

(TXCARRIERERROR)—Offset 160h........................................................... 361

15.6.40MMC Transmit Good Octet Counter Register (TXOCTETCOUNT_G)—Offset

164h ................................................................................................... 362

15.6.41MMC Transmit Good Frame Counter Register (TXFRAMECOUNT_G)—Offset

168h ................................................................................................... 362

15.6.42MMC Transmit Excessive Deferral Frame Counter Register (TXEXCESSDEF)—

Offset 16Ch ......................................................................................... 363

15.6.43MMC Transmit Pause Frame Counter Register (TXPAUSEFRAMES)—Offset

170h ................................................................................................... 363

15.6.44MMC Transmit VLAN Good Frame Counter Register

(TXVLANFRAMES_G)—Offset 174h .......................................................... 364

15.6.45MMC Transmit Oversize Good Frame Counter Register

(TXOVERSIZE_G)—Offset 178h............................................................... 364

15.6.46MMC Receive Good Bad Frame Counter Register

(RXFRAMECOUNT_GB)—Offset 180h........................................................ 364

15.6.47MMC Receive Good Bad Octet Counter Register

(RXOCTETCOUNT_GB)—Offset 184h........................................................ 365

15.6.48MMC Receive Good Octet Counter Register (RXOCTETCOUNT_G)—Offset

188h ................................................................................................... 365

15.6.49MMC Receive Broadcast Good Frame Counter Register

(RXBROADCASTFRAMES_G)—Offset 18Ch ................................................ 366

15.6.50MMC Receive Multicast Good Frame Counter Register

(RXMULTICASTFRAMES_G)—Offset 190h ................................................. 366

15.6.51MMC Receive CRC Error Frame Counter Register (RXCRCERROR)—Offset

194h ................................................................................................... 367

Intel® Quark SoC X1000

DS

12

October 2013

Document Number: 329676-001US

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