DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
16.6.1.18IN Endpoint 2 Write Confirmation register (for Slave-Only mode)
(ep2_wr_cfrm_udc_reg)—Offset 5Ch ......................................... 490
16.6.1.19IN Endpoint 3 Control Register (ep3_in_ctrl_udc_reg)—Offset 60h . 490
16.6.1.20IN Endpoint 3 Status Register (ep3_in_sts_udc_reg)—Offset 64h... 491
16.6.1.21IN Endpoint 3 Buffer Size Register
(ep3_in_bufsize_udc_reg)—Offset 68h ....................................... 493
16.6.1.22IN Endpoint 3 Maximum Packet Size Register
(ep3_in_mpkt_sz_reg)—Offset 6Ch ........................................... 494
16.6.1.23IN Endpoint 3 Data Descriptor Pointer Register
(ep3_in_desptr_udc_reg)—Offset 74h ........................................ 494
16.6.1.24IN Endpoint 3 Write Confirmation register (for Slave-Only mode)
(ep3_wr_cfrm_udc_reg)—Offset 7Ch ......................................... 495
16.6.1.25OUT Endpoint 0 Control Register (ep0_out_ctrl_udc_reg)—Offset
200h ..................................................................................... 495
16.6.1.26OUT Endpoint 0 Status Register (ep0_out_sts_udc_reg)—Offset
204h ..................................................................................... 496
16.6.1.27OUT Endpoint 0 Receive Packet Frame Number Register
(ep0_out_rpf_udc_reg)—Offset 208h ......................................... 498
16.6.1.28OUT Endpoint 0 Buffer Size Register (ep0_out_bufsize_udc_reg)—
Offset 20Ch ............................................................................ 499
16.6.1.29OUT Endpoint 0 SETUP Buffer Pointer Register
(ep0_subptr_udc_reg)—Offset 210h .......................................... 499
16.6.1.30OUT Endpoint 0 Data Descriptor Pointer Register
(ep0_out_desptr_udc_reg)—Offset 214h .................................... 500
16.6.1.31OUT Endpoint 0 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep0_rd_cfrm_udc_reg)—Offset 21Ch . 500
16.6.1.32OUT Endpoint 1 Control Register (ep1_out_ctrl_udc_reg)—Offset
220h ..................................................................................... 501
16.6.1.33OUT Endpoint 1 Status Register (ep1_out_sts_udc_reg)—Offset
224h ..................................................................................... 502
16.6.1.34OUT Endpoint 1 Receive Packet Frame Number Register
(ep1_out_rpf_udc_reg)—Offset 228h ......................................... 504
16.6.1.35OUT Endpoint 1 Buffer Size Register (ep1_out_bufsize_udc_reg)—
Offset 22Ch ............................................................................ 505
16.6.1.36OUT Endpoint 1 SETUP Buffer Pointer Register
(ep1_subptr_udc_reg)—Offset 230h .......................................... 505
16.6.1.37OUT Endpoint 1 Data Descriptor Pointer Register
(ep1_out_desptr_udc_reg)—Offset 234h .................................... 506
16.6.1.38OUT Endpoint 1 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep1_rd_cfrm_udc_reg)—Offset 23Ch . 506
16.6.1.39OUT Endpoint 2 Control Register (ep2_out_ctrl_udc_reg)—Offset
240h ..................................................................................... 507
16.6.1.40OUT Endpoint 2 Status Register (ep2_out_sts_udc_reg)—Offset
244h ..................................................................................... 508
16.6.1.41OUT Endpoint 2 Receive Packet Frame Number Register
(ep2_out_rpf_udc_reg)—Offset 248h ......................................... 510
16.6.1.42OUT Endpoint 2 Buffer Size Register (ep2_out_bufsize_udc_reg)—
Offset 24Ch ............................................................................ 511
16.6.1.43OUT Endpoint 2 SETUP Buffer Pointer Register
(ep2_subptr_udc_reg)—Offset 250h .......................................... 511
16.6.1.44OUT Endpoint 2 Data Descriptor Pointer Register
(ep2_out_desptr_udc_reg)—Offset 254h .................................... 512
16.6.1.45OUT Endpoint 2 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep2_rd_cfrm_udc_reg)—Offset 25Ch . 512
16.6.1.46OUT Endpoint 3 Control Register (ep3_out_ctrl_udc_reg)—Offset
260h ..................................................................................... 513
16.6.1.47OUT Endpoint 3 Status Register (ep3_out_sts_udc_reg)—Offset
264h ..................................................................................... 514
16.6.1.48OUT Endpoint 3 Receive Packet Frame Number Register
(ep3_out_rpf_udc_reg)—Offset 268h ......................................... 516
Intel® Quark SoC X1000
DS
18
October 2013
Document Number: 329676-001US
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