DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
16.6
16.5.3.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .... 460
16.5.3.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ......................... 461
16.5.3.7 Latency Timer (LATENCY_TIMER)—Offset Dh .............................. 461
16.5.3.8 Header Type (HEADER_TYPE)—Offset Eh ................................... 461
16.5.3.9 BIST (BIST)—Offset Fh ............................................................ 462
16.5.3.10Base Address Register (BAR0)—Offset 10h ................................. 462
16.5.3.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ......... 463
16.5.3.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ......... 463
16.5.3.13Subsystem ID (SUB_SYS_ID)—Offset 2Eh.................................. 464
16.5.3.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h 464
16.5.3.15Capabilities Pointer (CAP_POINTER)—Offset 34h ......................... 465
16.5.3.16Interrupt Line Register (INTR_LINE)—Offset 3Ch......................... 465
16.5.3.17Interrupt Pin Register (INTR_PIN)—Offset 3Dh ........................... 465
16.5.3.18MIN_GNT (MIN_GNT)—Offset 3Eh ............................................. 466
16.5.3.19MAX_LAT (MAX_LAT)—Offset 3Fh ............................................. 466
16.5.3.20Capability ID (PM_CAP_ID)—Offset 80h ..................................... 466
16.5.3.21Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h .............. 467
16.5.3.22Power Management Capabilities (PMC)—Offset 82h ..................... 467
16.5.3.23Power Management Control/Status Register (PMCSR)—Offset 84h . 468
16.5.3.24PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h....................................................................................... 469
16.5.3.25Power Management Data Register (DATA_REGISTER)—Offset 87h. 469
16.5.3.26Capability ID (MSI_CAP_ID)—Offset A0h.................................... 469
16.5.3.27Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ............ 470
16.5.3.28Message Control (MESSAGE_CTRL)—Offset A2h .......................... 470
16.5.3.29Message Address (MESSAGE_ADDR)—Offset A4h ........................ 470
16.5.3.30Message Data (MESSAGE_DATA)—Offset A8h ............................. 471
16.5.3.31Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ........................ 471
16.5.3.32Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ..................... 472
Memory Mapped Registers................................................................................ 472
16.6.1 USB Device ......................................................................................... 472
16.6.1.1 IN Endpoint 0 Control Register (ep0_in_ctrl_udc_reg)—Offset 0h .. 475
16.6.1.2 IN Endpoint 0 Status Register (ep0_in_sts_udc_reg)—Offset 4h .... 476
16.6.1.3 IN Endpoint 0 Buffer Size Register
(ep0_in_bufsize_udc_reg)—Offset 8h ........................................ 478
16.6.1.4 IN Endpoint 0 Maximum Packet Size Register
(ep0_in_mpkt_sz_reg)—Offset Ch............................................. 479
16.6.1.5 IN Endpoint 0 Data Descriptor Pointer Register
(ep0_in_desptr_udc_reg)—Offset 14h ....................................... 479
16.6.1.6 IN Endpoint 0 Write Confirmation register (for Slave-Only mode)
(ep0_wr_cfrm_udc_reg)—Offset 1Ch ......................................... 480
16.6.1.7 IN Endpoint 1 Control Register (ep1_in_ctrl_udc_reg)—Offset 20h 480
16.6.1.8 IN Endpoint 1 Status Register (ep1_in_sts_udc_reg)—Offset 24h .. 481
16.6.1.9 IN Endpoint 1 Buffer Size Register
(ep1_in_bufsize_udc_reg)—Offset 28h....................................... 483
16.6.1.10IN Endpoint 1 Maximum Packet Size Register
(ep1_in_mpkt_sz_reg)—Offset 2Ch ........................................... 484
16.6.1.11IN Endpoint 1 Data Descriptor Pointer Register
(ep1_in_desptr_udc_reg)—Offset 34h ....................................... 484
16.6.1.12IN Endpoint 1 Write Confirmation register (for Slave-Only mode)
(ep1_wr_cfrm_udc_reg)—Offset 3Ch ......................................... 485
16.6.1.13IN Endpoint 2 Control Register (ep2_in_ctrl_udc_reg)—Offset 40h 485
16.6.1.14IN Endpoint 2 Status Register (ep2_in_sts_udc_reg)—Offset 44h .. 486
16.6.1.15IN Endpoint 2 Buffer Size Register
(ep2_in_bufsize_udc_reg)—Offset 48h....................................... 488
16.6.1.16IN Endpoint 2 Maximum Packet Size Register
(ep2_in_mpkt_sz_reg)—Offset 4Ch ........................................... 489
16.6.1.17IN Endpoint 2 Data Descriptor Pointer Register
(ep2_in_desptr_udc_reg)—Offset 54h ....................................... 489
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
17
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