DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—

15.6.81MMC Receive IPV6 No Payload Frame Counter Register

(RXIPV6_NOPAY_FRMS)—Offset 22Ch ..................................................... 383

15.6.82MMC Receive UDP Good Frame Counter Register (RXUDP_GD_FRMS)—Offset

230h ................................................................................................... 384

15.6.83MMC Receive UDP Error Frame Counter Register

(RXUDP_ERR_FRMS)—Offset 234h .......................................................... 384

15.6.84MMC Receive TCP Good Frame Counter Register (RXTCP_GD_FRMS)—Offset

238h ................................................................................................... 385

15.6.85MMC Receive TCP Error Frame Counter Register (RXTCP_ERR_FRMS)—Offset

23Ch................................................................................................... 385

15.6.86MMC Receive ICMP Good Frame Counter Register

(RXICMP_GD_FRMS)—Offset 240h .......................................................... 386

15.6.87MMC Receive ICMP Error Frame Counter Register

(RXICMP_ERR_FRMS)—Offset 244h......................................................... 386

15.6.88MMC Receive IPV4 Good Octet Counter Register

(RXIPV4_GD_OCTETS)—Offset 250h ....................................................... 386

15.6.89MMC Receive IPV4 Header Error Octet Counter Register

(RXIPV4_HDRERR_OCTETS)—Offset 254h ................................................ 387

15.6.90MMC Receive IPV4 No Payload Octet Counter Register

(RXIPV4_NOPAY_OCTETS)—Offset 258h .................................................. 387

15.6.91MMC Receive IPV4 Fragmented Octet Counter Register

(RXIPV4_FRAG_OCTETS)—Offset 25Ch .................................................... 388

15.6.92MMC Receive IPV4 UDP Checksum Disabled Octet Counter Register

(RXIPV4_UDSBL_OCTETS)—Offset 260h .................................................. 388

15.6.93MMC Receive IPV6 Good Octet Counter Register

(RXIPV6_GD_OCTETS)—Offset 264h ....................................................... 389

15.6.94MMC Receive IPV6 Good Octet Counter Register (RXIPV6_HDRERR_OCTETS)—

Offset 268h.......................................................................................... 389

15.6.95MMC Receive IPV6 Header Error Octet Counter Register

(RXIPV6_NOPAY_OCTETS)—Offset 26Ch .................................................. 390

15.6.96MMC Receive IPV6 No Payload Octet Counter Register (RXUDP_GD_OCTETS)—

Offset 270h.......................................................................................... 390

15.6.97MMC Receive UDP Good Octet Counter Register

(RXUDP_ERR_OCTETS)—Offset 274h....................................................... 390

15.6.98MMC Receive TCP Good Octet Counter Register

(RXTCP_GD_OCTETS)—Offset 278h ........................................................ 391

15.6.99MMC Receive TCP Error Octet Counter Register

(RXTCP_ERR_OCTETS)—Offset 27Ch ....................................................... 391

15.6.100MMC Receive ICMP Good Octet Counter Register

(RXICMP_GD_OCTETS)—Offset 280h....................................................... 392

15.6.101MMC Receive ICMP Error Octet Counter Register

(RXICMP_ERR_OCTETS)—Offset 284h ..................................................... 392

15.6.102VLAN Tag Inclusion or Replacement Register (Register 353)

(GMAC_REG_353)—Offset 584h.............................................................. 393

15.6.103VLAN Hash Table Register (Register 354) (GMAC_REG_354)—Offset 588h .. 394

15.6.104Timestamp Control Register (Register 448) (GMAC_REG_448)—Offset 700h 394

15.6.105Sub-Second Increment Register (Register 449) (GMAC_REG_449)—Offset

704h ................................................................................................... 396

15.6.106System Time - Seconds Register (Register 450) (GMAC_REG_450)—Offset

708h ................................................................................................... 396

15.6.107System Time - Nanoseconds Register (Register 451)

(GMAC_REG_451)—Offset 70Ch ............................................................. 397

15.6.108System Time - Seconds Update Register (Register 452) (GMAC_REG_452)—

Offset 710h.......................................................................................... 397

15.6.109System Time - Nanoseconds Update Register (Register 453)

(GMAC_REG_453)—Offset 714h.............................................................. 398

15.6.110Timestamp Addend Register (Register 454) (GMAC_REG_454)—Offset 718h398

Intel® Quark SoC X1000

DS

14

October 2013

Document Number: 329676-001US

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