DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
16.6.1.49OUT Endpoint 3 Buffer Size Register (ep3_out_bufsize_udc_reg)—
Offset 26Ch ........................................................................... 517
16.6.1.50OUT Endpoint 3 SETUP Buffer Pointer Register
(ep3_subptr_udc_reg)—Offset 270h .......................................... 517
16.6.1.51OUT Endpoint 3 Data Descriptor Pointer Register
(ep3_out_desptr_udc_reg)—Offset 274h.................................... 518
16.6.1.52OUT Endpoint 3 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep3_rd_cfrm_udc_reg)—Offset 27Ch. 518
16.6.1.53Device Configuration Register (d_cfg_udc_reg)—Offset 400h ........ 519
16.6.1.54Device Control Register (d_ctrl_udc_reg)—Offset 404h ................ 520
16.6.1.55Device Status Register (d_sts_udc_reg)—Offset 408h .................. 522
16.6.1.56Device Interrupt Register (d_intr_udc_reg)—Offset 40Ch ............. 523
16.6.1.57Device Interrupt Mask Register (d_intr_msk_udc_reg)—Offset
410h ..................................................................................... 524
16.6.1.58Endpoints Interrupt Register (ep_intr_udc_reg)—Offset 414h ....... 525
16.6.1.59Endpoints Interrupt Mask Register (ep_intr_msk_udc_reg)—Offset
418h ..................................................................................... 525
16.6.1.60Test Mode Register (test_mode_udc_reg)—Offset 41Ch ............... 526
16.6.1.61Product Release Number Register (revision_udc_reg)—Offset 420h 527
16.6.1.62SETUP command address pointer register
(udc_desc_addr_udc_reg)—Offset 500h..................................... 527
16.6.1.63Physical Endpoint 0 Register (udc_ep_ne_udc_reg_0)—Offset 504h528
16.6.1.64Physical Endpoint 1 Register (udc_ep_ne_udc_reg_1)—Offset 508h528
16.6.1.65Physical Endpoint 2 Register (udc_ep_ne_udc_reg_2)—Offset
50Ch..................................................................................... 529
16.6.1.66Physical Endpoint 3 Register (udc_ep_ne_udc_reg_3)—Offset 510h530
16.6.1.67Physical Endpoint 4 Register (udc_ep_ne_udc_reg_4)—Offset 514h531
16.6.1.68Physical Endpoint 5 Register (udc_ep_ne_udc_reg_5)—Offset 518h532
16.6.1.69Physical Endpoint 6 Register (udc_ep_ne_udc_reg_6)—Offset
51Ch..................................................................................... 532
16.6.1.70RxFIFO Array[0-511] (udc_rx_fifo_reg_array[0-511])—Offset
800h, Count 512, Stride 4h ...................................................... 533
16.6.1.71TxFIFO 0 Array[0-255] (udc_tx_fifo_reg_0_array[0-255])—Offset
1000h, Count 256, Stride 4h .................................................... 534
16.6.1.72TxFIFO 1 Array[0-255] (udc_tx_fifo_reg_1_array[0-255])—Offset
1400h, Count 256, Stride 4h .................................................... 534
16.6.1.73TxFIFO 2 Array[0-255] (udc_tx_fifo_reg_2_array[0-255])—Offset
1800h, Count 256, Stride 4h .................................................... 534
16.6.1.74TxFIFO 3 Array[0-255] (udc_tx_fifo_reg_3_array[0-255])—Offset
1C00h, Count 256, Stride 4h .................................................... 535
16.6.2 USB EHCI............................................................................................ 535
16.6.2.1 Host Controller Interface Version Number and Capability Registers
Length (HCCAPBASE)—Offset 0h............................................... 536
16.6.2.2 Host Controller Structural Parameters (HCSPARAMS)—Offset 4h ... 536
16.6.2.3 Host Controller Capability Parameters (HCCPARAMS)—Offset 8h ... 538
16.6.2.4 USB Command (USBCMD)—Offset 10h ...................................... 539
16.6.2.5 USB Status (USBSTS)—Offset 14h ............................................ 541
16.6.2.6 USB Interrupt Enable (USBINTR)—Offset 18h ............................. 543
16.6.2.7 USB Frame Index (FRINDEX)—Offset 1Ch .................................. 544
16.6.2.8 4 Gigabyte Memory Segment Selector (CTRLDSSEGMENT)—Offset
20h....................................................................................... 545
16.6.2.9 Periodic Frame List Base Address (PERIODICLISTBASE)—Offset
24h....................................................................................... 545
16.6.2.10Asynchronous List Address (ASYNCLISTADDR)—Offset 28h .......... 546
16.6.2.11Configure Flag (CONFIGFLAG)—Offset 50h ................................. 546
16.6.2.12Port Status/Control[0-1] (PORTSC[0-1])—Offset 54h, Count 2,
Stride 4h ............................................................................... 547
16.6.2.13Programmable Microframe Base Value (INSNREG00)—Offset 90h .. 550
16.6.2.14Programmable Packet Buffer OUT/IN Thresholds
(INSNREG01)—Offset 94h........................................................ 551
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
19
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