DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
16.5.1.18MIN_GNT (MIN_GNT)—Offset 3Eh ............................................. 432
16.5.1.19MAX_LAT (MAX_LAT)—Offset 3Fh .............................................. 432
16.5.1.20Capability ID (PM_CAP_ID)—Offset 80h...................................... 433
16.5.1.21Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h .............. 433
16.5.1.22Power Management Capabilities (PMC)—Offset 82h ...................... 433
16.5.1.23Power Management Control/Status Register (PMCSR)—Offset 84h . 434
16.5.1.24PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h ....................................................................................... 435
16.5.1.25Power Management Data Register (DATA_REGISTER)—Offset 87h . 435
16.5.1.26Capability ID (MSI_CAP_ID)—Offset A0h .................................... 436
16.5.1.27Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ............. 436
16.5.1.28Message Control (MESSAGE_CTRL)—Offset A2h .......................... 436
16.5.1.29Message Address (MESSAGE_ADDR)—Offset A4h ........................ 437
16.5.1.30Message Data (MESSAGE_DATA)—Offset A8h ............................. 437
16.5.1.31Mask Bits for MSI (PER_VEC_MASK)—Offset ACh......................... 438
16.5.1.32Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ..................... 438
16.5.2 USB EHCI ............................................................................................ 439
16.5.2.1 Vendor ID (VENDOR_ID)—Offset 0h .......................................... 440
16.5.2.2 Device ID (DEVICE_ID)—Offset 2h ............................................ 440
16.5.2.3 Command Register (COMMAND_REGISTER)—Offset 4h ................ 440
16.5.2.4 Status Register (STATUS)—Offset 6h ......................................... 441
16.5.2.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .... 442
16.5.2.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ......................... 442
16.5.2.7 Latency Timer (LATENCY_TIMER)—Offset Dh .............................. 443
16.5.2.8 Header Type (HEADER_TYPE)—Offset Eh .................................... 443
16.5.2.9 BIST (BIST)—Offset Fh ............................................................ 443
16.5.2.10Base Address Register (BAR0)—Offset 10h ................................. 444
16.5.2.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ......... 445
16.5.2.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch.......... 445
16.5.2.13Subsystem ID (SUB_SYS_ID)—Offset 2Eh .................................. 445
16.5.2.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h. 446
16.5.2.15Capabilities Pointer (CAP_POINTER)—Offset 34h.......................... 446
16.5.2.16Interrupt Line Register (INTR_LINE)—Offset 3Ch ......................... 446
16.5.2.17Interrupt Pin Register (INTR_PIN)—Offset 3Dh ............................ 447
16.5.2.18MIN_GNT (MIN_GNT)—Offset 3Eh ............................................. 447
16.5.2.19MAX_LAT (MAX_LAT)—Offset 3Fh .............................................. 448
16.5.2.20Serial Bus Release Number Register (SBRN)—Offset 60h .............. 448
16.5.2.21Frame Length Adjustment Register (FLADJ)—Offset 61h ............... 448
16.5.2.22Capability ID (PM_CAP_ID)—Offset 80h...................................... 449
16.5.2.23Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h .............. 449
16.5.2.24Power Management Capabilities (PMC)—Offset 82h ...................... 449
16.5.2.25Power Management Control/Status Register (PMCSR)—Offset 84h . 450
16.5.2.26PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h ....................................................................................... 451
16.5.2.27Power Management Data Register (DATA_REGISTER)—Offset 87h . 451
16.5.2.28Capability ID (MSI_CAP_ID)—Offset A0h .................................... 451
16.5.2.29Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ............. 452
16.5.2.30Message Control (MESSAGE_CTRL)—Offset A2h .......................... 452
16.5.2.31Message Address (MESSAGE_ADDR)—Offset A4h ........................ 453
16.5.2.32Message Data (MESSAGE_DATA)—Offset A8h ............................. 453
16.5.2.33Mask Bits for MSI (PER_VEC_MASK)—Offset ACh......................... 454
16.5.2.34Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ..................... 454
16.5.2.35USB Legacy Support Extended Capability (USBLEGSUP)—Offset
C0h ....................................................................................... 454
16.5.2.36USB Legacy Support Control/Status (USBLEGCTLSTS)—Offset C4h 455
16.5.3 USB OHCI............................................................................................ 457
16.5.3.1 Vendor ID (VENDOR_ID)—Offset 0h .......................................... 458
16.5.3.2 Device ID (DEVICE_ID)—Offset 2h ............................................ 458
16.5.3.3 Command Register (COMMAND_REGISTER)—Offset 4h ................ 459
16.5.3.4 Status Register (STATUS)—Offset 6h ......................................... 459
Intel® Quark SoC X1000
DS
16
October 2013
Document Number: 329676-001US
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