DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
| |||
Intel® Quark SoC X1000—
16.6.2.15Programmable Packet Buffer Depth (INSNREG02)—Offset 98h ...... 551
16.6.2.16Programmable Controller Settings (INSNREG03)—Offset 9Ch ........ 552
16.6.2.17Programmable Controller Settings (INSNREG04)—Offset A0h ........ 553
16.6.2.18UTMI Configuration (INSNREG05)—Offset A4h ............................ 554
16.6.3 USB OHCI............................................................................................ 555
16.6.3.1 OHCI Revision (HCREVISION)—Offset 0h.................................... 556
16.6.3.2 Host Controller Control (HCCONTROL)—Offset 4h ........................ 556
16.6.3.3 Host Controller Command Status (HCCMDSTATUS)—Offset 8h ...... 557
16.6.3.4 Host Controller Interrupt Status (HCINTRSTATUS)—Offset Ch ....... 559
16.6.3.5 Host Controller Interrupt Enable (HCINTRENABLE)—Offset 10h...... 560
16.6.3.6 Host Controller Interrupt Disable (HCINTRDISABLE)—Offset 14h ... 561
16.6.3.7 Host Controller Communication Area (HCHCCA)—Offset 18h ......... 562
16.6.3.8 Host Controller Current Isochronous or Interrupt Endpoint
(HCPRDCURED)—Offset 1Ch ..................................................... 563
16.6.3.9 Host Controller Current First Control Endpoint (HCCTRLHEADED)—
Offset 20h .............................................................................. 563
16.6.3.10Host Controller Current Control Endpoint (HCCTRLCURED)—Offset
24h ....................................................................................... 564
16.6.3.11Host Controller First Bulk Endpoint (HCBULKHEADED)—Offset 28h . 564
16.6.3.12Host Controller Current Bulk Endpoint (HCBULKCURED)—Offset
2Ch ....................................................................................... 565
16.6.3.13Host Controller Last Completed Descriptor (HCDONEHEAD)—Offset
30h ....................................................................................... 566
16.6.3.14Host Controller Frame Interval (HCFMINTERVAL)—Offset 34h........ 566
16.6.3.15Host Controller Remaining Frame (HCFMREMAINING)—Offset 38h . 567
16.6.3.16Host Controller Frame Number (HCFMNUMBER)—Offset 3Ch ......... 568
16.6.3.17Host Controller Periodic List Start (HCPERIODICSTART)—Offset
40h ....................................................................................... 569
16.6.3.18Host Controller LS Threshold (HCLSTHRESHOLD)—Offset 44h ....... 569
16.6.3.19Host Controller Root Hub Descriptor A (HCRHDESPA)—Offset 48h .. 570
16.6.3.20Host Controller Root Hub Descriptor B (HCRHDESPB)—Offset 4Ch.. 571
16.6.3.21Host Controller Root Hub Status (HCRHSTATUS)—Offset 50h ........ 572
16.6.3.22Host Controller Root Hub Port Status (HCRHPORTSTS)—Offset 54h 573
17.0 SDIO/SD/eMMC ..................................................................................................... 577
17.1 Signal Descriptions .......................................................................................... 577
17.2 Features ......................................................................................................... 578
17.2.1 SDIO/SD/eMMC Features ....................................................................... 578
17.2.2 SD 3.0/ SDIO 3.0 / eMMC 4.41 Interfaces ................................................ 578
17.2.2.1 SD 3.0 Bus Topology ............................................................... 578
17.2.2.2 SDIO 3.0 Interface .................................................................. 579
17.2.2.3 eMMC Interface....................................................................... 580
17.2.3 SDIO/SD/eMMC Host Controller .............................................................. 580
17.2.3.1 SD DMA ................................................................................. 581
17.3 References...................................................................................................... 581
17.4 Register Map................................................................................................... 581
17.5 PCI Configuration Registers............................................................................... 582
17.5.1 Vendor ID (VENDOR_ID)—Offset 0h ........................................................ 583
17.5.2 Device ID (DEVICE_ID)—Offset 2h .......................................................... 584
17.5.3 Command Register (COMMAND_REGISTER)—Offset 4h .............................. 584
17.5.4 Status Register (STATUS)—Offset 6h....................................................... 585
17.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .................. 585
17.5.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ....................................... 586
17.5.7 Latency Timer (LATENCY_TIMER)—Offset Dh ............................................ 586
17.5.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 587
17.5.9 BIST (BIST)—Offset Fh .......................................................................... 587
17.5.10Base Address Register (BAR0)—Offset 10h ............................................... 588
17.5.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h....................... 588
Intel® Quark SoC X1000
DS
20
October 2013
Document Number: 329676-001US
Share Link: 