DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

—Intel® Quark SoC X1000

15.6.52MMC Receive Alignment Error Frame Counter Register

(RXALIGNMENTERROR)—Offset 198h ...................................................... 367

15.6.53MMC Receive Runt Frame Counter Register (RXRUNTERROR)—Offset 19Ch .. 368

15.6.54MMC Receive Jabber Error Frame Counter Register

(RXJABBERERROR)—Offset 1A0h ............................................................ 368

15.6.55MMC Receive Undersize Good Frame Counter Register

(RXUNDERSIZE_G)—Offset 1A4h............................................................ 368

15.6.56MMC Receive Oversize Good Frame Counter Register

(RXOVERSIZE_G)—Offset 1A8h.............................................................. 369

15.6.57MMC Receive 64 Octet Good Bad Frame Counter Register

(RX64OCTETS_GB)—Offset 1ACh ........................................................... 369

15.6.58MMC Receive 65 to 127 Octet Good Bad Frame Counter Register

(RX65TO127OCTETS_GB)—Offset 1B0h................................................... 370

15.6.59MMC Receive 128 to 255 Octet Good Bad Frame Counter Register

(RX128TO255OCTETS_GB)—Offset 1B4h ................................................. 370

15.6.60MMC Receive 256 to 511 Octet Good Bad Frame Counter Register

(RX256TO511OCTETS_GB)—Offset 1B8h ................................................. 371

15.6.61MMC Receive 512 to 1023 Octet Good Bad Frame Counter Register

(RX512TO1023OCTETS_GB)—Offset 1BCh ............................................... 371

15.6.62MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Register

(RX1024TOMAXOCTETS_GB)—Offset 1C0h .............................................. 372

15.6.63MMC Receive Unicast Good Frame Counter Register (RXUNICASTFRAMES_G)—

Offset 1C4h ......................................................................................... 372

15.6.64MMC Receive Length Error Frame Counter Register

(RXLENGTHERROR)—Offset 1C8h ........................................................... 372

15.6.65MMC Receive Out Of Range Error Frame Counter Register

(RXOUTOFRANGETYPE)—Offset 1CCh...................................................... 373

15.6.66MMC Receive Pause Frame Counter Register (RXPAUSEFRAMES)—Offset

1D0h .................................................................................................. 373

15.6.67MMC Receive FIFO Overflow Frame Counter Register

(RXFIFOOVERFLOW)—Offset 1D4h.......................................................... 374

15.6.68MMC Receive VLAN Good Bad Frame Counter Register (RXVLANFRAMES_GB)—

Offset 1D8h......................................................................................... 374

15.6.69MMC Receive Watchdog Error Frame Counter Register

(RXWATCHDOGERROR)—Offset 1DCh ..................................................... 375

15.6.70MMC Receive Error Frame Counter Register (RXRCVERROR)—Offset 1E0h .... 375

15.6.71MMC Receive Control Frame Counter Register (RXCTRLFRAMES_G)—Offset

1E4h .................................................................................................. 376

15.6.72MMC IPC Receive Checksum Offload Interrupt Mask Register

(MMC_IPC_INTR_MASK_RX)—Offset 200h ............................................... 376

15.6.73MMC Receive Checksum Offload Interrupt Register

(MMC_IPC_INTR_RX)—Offset 208h......................................................... 378

15.6.74MMC Receive IPV4 Good Frame Counter Register

(RXIPV4_GD_FRMS)—Offset 210h .......................................................... 380

15.6.75MMC Receive IPV4 Header Error Frame Counter Register

(RXIPV4_HDRERR_FRMS)—Offset 214h ................................................... 381

15.6.76MMC Receive IPV4 No Payload Frame Counter Register

(RXIPV4_NOPAY_FRMS)—Offset 218h ..................................................... 381

15.6.77MMC Receive IPV4 Fragmented Frame Counter Register

(RXIPV4_FRAG_FRMS)—Offset 21Ch ....................................................... 382

15.6.78MMC Receive IPV4 UDP Checksum Disabled Frame Counter Register

(RXIPV4_UDSBL_FRMS)—Offset 220h ..................................................... 382

15.6.79MMC Receive IPV6 Good Frame Counter Register

(RXIPV6_GD_FRMS)—Offset 224h .......................................................... 382

15.6.80MMC Receive IPV6 Header Error Frame Counter Register

(RXIPV6_HDRERR_FRMS)—Offset 228h ................................................... 383

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

13

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