DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
15.6.111Target Time Seconds Register (Register 455) (GMAC_REG_455)—Offset
71Ch .................................................................................................. 399
15.6.112Target Time Nanoseconds Register (Register 456)
(GMAC_REG_456)—Offset 720h ............................................................. 399
15.6.113System Time - Higher Word Seconds Register (Register 457)
(GMAC_REG_457)—Offset 724h ............................................................. 400
15.6.114Timestamp Status Register (Register 458) (GMAC_REG_458)—Offset 728h 401
15.6.115Bus Mode Register (Register 0) (DMA_REG_0)—Offset 1000h ................... 402
15.6.116Transmit Poll Demand Register (Register 1) (DMA_REG_1)—Offset 1004h .. 404
15.6.117Receive Poll Demand Register (Register 2) (DMA_REG_2)—Offset 1008h.... 404
15.6.118Receive Descriptor List Address Register (Register 3) (DMA_REG_3)—Offset
100Ch ................................................................................................ 405
15.6.119Transmit Descriptor List Address Register (Register 4)
(DMA_REG_4)—Offset 1010h ................................................................. 405
15.6.120Status Register (Register 5) (DMA_REG_5)—Offset 1014h........................ 406
15.6.121Operation Mode Register (Register 6) (DMA_REG_6)—Offset 1018h........... 409
15.6.122Interrupt Enable Register (Register 7) (DMA_REG_7)—Offset 101Ch.......... 412
15.6.123Missed Frame and Buffer Overflow Counter Register (Register 8)
(DMA_REG_8)—Offset 1020h ................................................................. 413
15.6.124Receive Interrupt Watchdog Timer Register (Register 9)
(DMA_REG_9)—Offset 1024h ................................................................. 414
15.6.125AHB Status Register (Register 11) (DMA_REG_11)—Offset 102Ch ............. 414
15.6.126Current Host Transmit Descriptor Register (Register 18)
(DMA_REG_18)—Offset 1048h ............................................................... 415
15.6.127Current Host Receive Descriptor Register (Register 19)
(DMA_REG_19)—Offset 104Ch ............................................................... 415
15.6.128Current Host Transmit Buffer Address Register (Register 20)
(DMA_REG_20)—Offset 1050h ............................................................... 416
15.6.129Current Host Receive Buffer Address Register (Register 21) (DMA_REG_21)—
Offset 1054h ....................................................................................... 416
15.6.130HW Feature Register (Register 22) (DMA_REG_22)—Offset 1058h ............. 417
16.0 USB 2.0 ................................................................................................................. 421
16.1 Signal Descriptions .......................................................................................... 421
16.2 Features ........................................................................................................ 421
16.2.1 USB2.0 Host Controller Features ............................................................ 421
16.2.2 USB2.0 Device Features ........................................................................ 422
16.3 References ..................................................................................................... 422
16.4 Register Map .................................................................................................. 423
16.5 PCI Configuration Registers .............................................................................. 423
16.5.1 USB Device ......................................................................................... 423
16.5.1.1 Vendor ID (VENDOR_ID)—Offset 0h .......................................... 424
16.5.1.2 Device ID (DEVICE_ID)—Offset 2h ............................................ 425
16.5.1.3 Command Register (COMMAND_REGISTER)—Offset 4h ................ 425
16.5.1.4 Status Register (STATUS)—Offset 6h......................................... 426
16.5.1.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .... 426
16.5.1.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ......................... 427
16.5.1.7 Latency Timer (LATENCY_TIMER)—Offset Dh .............................. 427
16.5.1.8 Header Type (HEADER_TYPE)—Offset Eh ................................... 428
16.5.1.9 BIST (BIST)—Offset Fh ............................................................ 428
16.5.1.10Base Address Register (BAR0)—Offset 10h ................................. 429
16.5.1.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ......... 429
16.5.1.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ......... 430
16.5.1.13Subsystem ID (SUB_SYS_ID)—Offset 2Eh.................................. 430
16.5.1.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h 430
16.5.1.15Capabilities Pointer (CAP_POINTER)—Offset 34h ......................... 431
16.5.1.16Interrupt Line Register (INTR_LINE)—Offset 3Ch......................... 431
16.5.1.17Interrupt Pin Register (INTR_PIN)—Offset 3Dh ........................... 432
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
15
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