DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
Bit
Default &
Range Access
Description
C8-CF Enable (EC8): Enables decoding of BIOS range FFC80000h - FFCFFFFFh and
25
1b
RW
FF880000h - FF8FFFFFh.
0 = Disable
1 = Enable
C0-C8 Enable (EC0): Enables decoding of BIOS range FFC00000h - FFC7FFFFh and
24
1b
RW
FF800000h - FF87FFFFh.
0 = Disable
1 = Enable
23:0
0b
RO
Reserved (RSV): Reserved.
21.3.14
BIOS Control (BC)—Offset D8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
BC: [B:0, D:31, F:0] + D8h
Default: 00000100h
31
28
24
20
16
12
8
4
0
00000000000000000000000100000000
Bit
Default &
Range Access
Description
31:9
0b
RO
Reserved (RSV3): Reserved.
Prefetch Enable (PFE): When set, BIOS prefetching is enabled. An access to BIOS
8
1b
RW
causes a 64-byte fetch of the line starting at that region. Subsequent accesses within
that region result in data being returned from the prefetch buffer. The prefetch buffer is
invalidated when this bit is cleared, or a BIOS access occurs to a different line than what
is currently in the buffer
7:6
0b
RO
Reserved (RSV2): Reserved.
SMM Write Protect Disable (SMM_WPD): When LE is clear: Setting this bit has no
effect.
5
0b
RW
When LE is set: Setting this bit enables both read and write cycles to the SPI Flash,
clearing this bit blocks write cycles to the SPI Flash.
This bit is not writeable unless the processor is in SMM mode.
This bit must be cleared before the processor exits SMM mode to prevent write cycles to
SPI flash when the processor is in a non-SMM mode.
4:3
0b
RO
Reserved (RSV1): Reserved.
2
0b
RW
Cache Disable (CD): Enable caching in read buffer for direct memory read.
Lock Enable (LE): When cleared, setting the WPD bit will not generate SMIs and the
WPD bit is used to enable write cycles to the SPI Flash.
1
0b
RW/P
When set, enables setting the WPD bit to generate SMIs and the SMM_WPD bit is used
to enable write cycles to the SPI Flash.
Once set, this bit can only be cleared by a reset.
Intel® Quark SoC X1000
DS
812
October 2013
Document Number: 329676-001US
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