DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
21.5
21.5.1
IO Registers
The Legacy Bridge contains a mix of fixed address I/O Registers and I/O Registers that
are mapped by BARs in the Legacy Bridge configuration space. This sections describes
the Fixed I/O registers and the Legacy ACPI I/O Register.s All other I/O Registers are
described in the relevant sections later in this chapter.
Fixed IO Registers
Table 114. Summary of I/O Registers
Offset
Start
61h
70h
B2h
B3h
CF9h
Offset End
Register ID—Description
61h
70h
B2h
B3h
CF9h
“NMI Status and Control Register (NSC)—Offset 61h†on page 818
“NMI Enable and RTC Index Register (NMIE)—Offset 70h†on page 819
“Software SMI Control Port (SWSMICTL)—Offset B2h†on page 819
“Software SMI Status Port (SWSMISTS)—Offset B3h†on page 820
“Reset Control Register (RSTC)—Offset CF9h†on page 820
21.5.1.1 NMI Status and Control Register (NSC)—Offset 61h
Access Method
Type: I/O Register
(Size: 8 bits)
Default: 00h
7
4
0
0
0
0
0
0
Default
Value
00h
80h
00h
00h
00h
NSC: 61h
0
0
0
Bit
Default &
Range Access
Description
7
0b
RO
SERR# NMI Status (SERR_NMI_STATUS): Set on errors from a PCIe port or internal
functions that generate SERR#. SERR# NMI Enable in this register must be cleared in
order for this bit to be set. To reset the interrupt, set bit 2 to 1 and then set it to 0.
6
0b
RO
Reserved (RSVD): Reserved.
5
0b
RO
Timer Counter 2 Status (CNTR2_STATUS): Reflects the current state of the 8254
counter 2 output. Counter 2 must be programmed for this bit to have a determinate
value.
4
0b
RO
Refresh Cycle Toggle Status (CNTR1_TOGGLE_STATUS): Reflects the current state
of 8254 counter 1.
3
0b
RO
Reserved (RSVD): Reserved.
Intel® Quark SoC X1000
DS
818
October 2013
Document Number: 329676-001US
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