DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Bit
Default &
Range Access
Description
7:4
0b
RO
Reserved (RSV): Reserved.
3:0
2h
RO
Element Type (ETYPE): Indicates that the element type is a root complex internal link
21.4.1.3 Interrupt Queue Agent 0 (IRQAGENT0)—Offset 3140h
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
IRQAGENT0: [RCBA] + 3140h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
Default: 0000h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Default &
Range Access
Description
15:8
0b
RO
Reserved (RSV): Reserved.
7:4
0b
RW
Reserved (RSV_RW): Reserved.
3:0
0b
RW
Interrupt A Pin Route (INTAPR): Indicates which PIRQ routing used for INTA#. Legal
values are [0x0-0x7] corresponding to PIRQ[A-H]. For example, INTA# will be routed to
PIRQG if this field is set to 0x6.
21.4.1.4 Interrupt Queue Agent 1 (IRQAGENT1)—Offset 3142h
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
IRQAGENT1: [RCBA] + 3142h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
Default: 0000h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
815
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