DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Bit
Default &
Range Access
Description
2
0b
RW
SERR# NMI Enable (SERR_NMI_ENABLE): When set, SERR# NMIs are disabled.
When cleared, SERR# NMIs are enabled.
1
0b
RW
Speaker Data Enable (SPKR_ENABLE): When this bit is a 0, the SPKR output is a 0.
When this bit is a 1, the SPKR output is equivalent to the Counter 2 OUT signal value.
0
0b
RW
Timer Counter 2 Enable (CNTR2_ENABLE): When cleared, counter 2 counting is
disabled. When set, counting is enabled.
21.5.1.2
NMI Enable and RTC Index Register (NMIE)—Offset 70h
Access Method
Type: I/O Register
(Size: 8 bits)
Default: 80h
7
4
1
0
0
0
0
0
0
NMIE: 70h
0
0
Bit
Default &
Range Access
Description
7
1b
WO
NMI Enable (NMI_ENABLE): When set, NMI sources disabled. When cleared, NMI
sources enabled.
6:0
0b
WO
Real Time Clock Index (RTC_INDEX): Selects RTC register or CMOS RAM address to
access.
21.5.1.3
Software SMI Control Port (SWSMICTL)—Offset B2h
Access Method
Type: I/O Register
(Size: 8 bits)
Default: 00h
7
4
0
0
0
0
0
0
SWSMICTL: B2h
0
0
0
Bit
Default &
Range Access
Description
7:0
0b
RW
Software SMI Control Port (CONTROL): This port is used to pass a command
between the OS and the SMI handler. Writes to this port store data, set APM bit of SMI
Status register of GPE0 Block, and generate SMI# when APM is set.
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
819
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