DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
| |||
Legacy Bridge—Intel® Quark SoC X1000
Bit
Default &
Range Access
Description
Write Protect Disable (WPD): When LE is clear: Setting this bit enables both read
and write cycles into the SPI Flash, clearing this bit blocks write cycles to the SPI Flash.
0
0b
RW
When LE is set: Setting this bit will generate an SMI, the SMM_WPD bit must then be
used to enable write cycles to the SPI Flash.
This bit must be cleared before the processor exits SMM mode in order to clear the SMI
source.
21.3.15
Root Complex Base Address (RCBA)—Offset F0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
RCBA: [B:0, D:31, F:0] + F0h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:14
0b
RW
Base Address (BA): Base Address for the root complex register block decode range.
This address is aligned on a 16 KB boundary.
13:1
0b
RO
Reserved (RSV): Reserved.
0
0b
RW
Enable (EN): When set, enables the range specified in BA to be claimed as the RCRB.
21.4
Memory Mapped Registers
21.4.1
Root Complex Register Block
This block describes all registers and base functionality that are related to SoC
configuration but not a specific interface. It contains the root complex register block.
Accesses in this space are limited to 32-bit quantities. Burst accesses are not allowed.
Table 113. Summary of Memory Mapped I/O Registers—RCBA
Offset
Start
0h
4h
3140h
3142h
3144h
3146h
3400h
Offset End
Register ID—Description
3h
7h
3141h
3143h
3145h
3147h
3403h
“Root Complex Topology Capabilities List (RCTCL)—Offset 0h†on page 814
“Element Self Description (ESD)—Offset 4h†on page 814
“Interrupt Queue Agent 0 (IRQAGENT0)—Offset 3140h†on page 815
“Interrupt Queue Agent 1 (IRQAGENT1)—Offset 3142h†on page 815
“Interrupt Queue Agent 2 (IRQAGENT2)—Offset 3144h†on page 816
“Interrupt Queue Agent 3 (IRQAGENT3)—Offset 3146h†on page 816
“Root Complex Topology Capabilities List (RCTCL)—Offset 0h†on page 814
Default
Value
00010005h
00000102h
0000h
0000h
0000h
0000h
00000000h
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
813
Share Link: 