DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
21.5.1.4
Software SMI Status Port (SWSMISTS)—Offset B3h
Access Method
Type: I/O Register
(Size: 8 bits)
Default: 00h
7
4
0
0
0
0
0
0
SWSMISTS: B3h
0
0
0
Bit
Default &
Range Access
Description
7:0
0b
RW
Software SMI Status Port (STATUS): This port is used to pass data between the OS
and the SMI handler. This is a scratchpad register.
21.5.1.5 Reset Control Register (RSTC)—Offset CF9h
Access Method
Type: I/O Register
(Size: 8 bits)
Default: 00h
7
4
0
0
0
0
0
0
RSTC: CF9h
0
0
0
Bit
Default &
Range Access
Description
7:5
0b
RO
Reserved (RSV2): Reserved.
4
0b
RO
Reserved (RSVD): Reserved.
3
0b
RW
Cold Reset (COLD_RST): This bit causes SLPMODE, and RSTRDY# to be driven low,
while SLPRDY# remains high. In response to this, the platform will perform a full power
cycle
2
0b
RO
Reserved (RSV1): Reserved.
1
0b
RW
Warm Reset (WARM_RST): This bit causes RSTRDY# to be driven low, with SLPMODE
high, while SLPRDY# remains high. In response to this, the platform will pulse RESET#
low to reset the CPU and all peripherals
0
0b
RO
Reserved (RSVD): Reserved.
Intel® Quark SoC X1000
DS
820
October 2013
Document Number: 329676-001US
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