DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
Bit
Default &
Range Access
Description
31:0
0b
RW
Counter Value (CV): Reads return the current value of the upper 32 bits of the
counter. Writes load the new value to the upper 32 bits of the counter. Timers 1 and
Timer 2 return 0.
21.9.3.7
Timer 0 Config and Capabilities Register - Lower 32 Bits (T0C_1)—
Offset 100h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
T0C_1: [0xFED00000] + 100h
Default: 00000030h
31
28
24
20
16
12
8
4
0
00000000000000000000000000110000
Bit
Default &
Range Access
Description
31:16
0b
RO
Reserved (RSV3): Reserved.
15
0b
RO
FSB Interrupt Delivery (FID): Not Supported
14
0b
RO
FSB Enable (FE): Not supported, since FID is not supported.
Interrupt Route (IR): Indicates the routing for the interrupt to the IOxAPIC. If the
13:9
0b
RW
value is not supported by this particular timer, the value read back will not match what
is written. If GC.LRE is set, then Timers 0 and 1 have a fixed routing, and this field has
no effect.
8
0b
RW
Timer 32-bit Mode (T32M): When set, this bit forces a 64-bit timer to behave as a
32-bit timer.
7
0b
RO
Reserved (RSV2): Reserved.
6
0b
WO
Timer Value Set (TVS): This bit will return 0 when read. Writes will only have an effect
for Timer 0 if it is set to periodic mode. Writes will have no effect for Timers 1 and 2
5
1b
RO
Timer Size (TS): 1 = 64-bits, 0 = 32-bits. Set for timer 9. Cleared for timers 1 and 2
4
1b
RO
Periodic Interrupt Capable (PIC): When set, hardware supports a periodic mode for
this timer's interrupt.
3
0b
RW
Timer Type (TYP): If PIC is set, this bit is read/write, and can be used to enable the
timer to generate a periodic interrupt.
2
0b
RW
Interrupt Enable (IE): When set, enables the timer to cause an interrupt when it
times out. When cleared, the timer count and generates status bits, but will not cause
an interrupt.
Timer Interrupt Type (IT): When cleared, interrupt is edge triggered. When set,
1
0b
RW
interrupt is level triggered and will be held active until it is cleared by writing 1 to
GIS.Tn. If another interrupt occurs before the interrupt is cleared, the interrupt remains
active.
0
0b
RO
Reserved (RSV1): Reserved.
Intel® Quark SoC X1000
DS
872
October 2013
Document Number: 329676-001US
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