DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

Table 125.

RTC Signals

Signal Name

RTCX1

RTCX2

RTCRST_B

IVCCRTCEXT

RTC_EXT_CLK_EN_B

Direction/

Type

Description

I

Analog

I

Analog

I

CMOS3.3

I

Analog

I

CMOS3.3

Crystal Input 1: This signal is connected to the 32.768 KHz crystal.

Crystal Input 2: This signal is connected to the 32.768 KHz crystal.

RTC Reset: When asserted, this signal resets register bits in the RTC

well.

External Capacitor Connection

RTC Internal Clock Select: Used to select between the oscillator

clock from the external 32.768 KHz crystal or an internally generated

32.768 KHz clock.

0 = External 32.768 KHz oscillator

1 = Internal 32.768 KHz Clock (Default)

21.10.2 Features

The Real Time Clock (RTC) module provides a battery backed-up date and time keeping

device. Three interrupt features are available: time of day alarm with once a second to

once a month range, periodic rates of 122 ms to 500 ms, and end of update cycle

notification. Seconds, minutes, hours, days, day of week, month, and year are counted.

The hour is represented in twelve or twenty-four hour format, and data can be

represented in BCD or binary format. The design is meant to be functionally compatible

with the Motorola MS146818B. The time keeping comes from a 32.768 KHz oscillating

source, which is divided to achieve an update every second. The lower 14 bytes on the

lower RAM block have very specific functions. The first ten are for time and date

information. The next four (0Ah to 0Dh) are registers, which configure and report RTC

functions. A host-initiated write takes precedence over a hardware update in the event

of a collision.

21.10.2.1 Update Cycles

An update cycle occurs once a second, if the B.SET bit is not asserted and the divide

chain is properly configured. During this procedure, the stored time and date are

incremented, overflow checked, a matching alarm condition is checked, and the time

and date are rewritten to the RAM locations. The update cycle starts at least 488 ms

after A.UIP is asserted, and the entire cycle does not take more than 1984 ms to

complete. The time and date RAM locations (00h to 09h) are disconnected from the

external bus during this time.

21.10.2.2 Interrupts

The real-time clock interrupt is internally routed within the SoC both to the I/O APIC

and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the SoC,

nor is it shared with any other interrupt. However, the High Performance Event Timers

can also be mapped to IRQ8#; in this case, the RTC interrupt is blocked.

21.10.2.3 Lockable RAM Ranges

The RTC battery-backed RAM supports two 8-byte ranges that can be locked via the

RTC Configuration register. When the locking bits are set, the corresponding range in

the RAM is not readable or writable. A write cycle to those locations has no effect. A

read cycle to those locations does not return the location’s actual value (resultant value

is undefined).

Intel® Quark SoC X1000

DS

878

October 2013

Document Number: 329676-001US

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