DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
The first 14 bytes of the standard bank contain the RTC time and date information
along with four registers, A - D, that are used for configuration of the RTC. The
extended bank contains a full 128 bytes of battery backed SRAM. All data movement
between the host CPU and the RTC is done through registers mapped to the standard I/
O space.
Note:
It is not possible to disable the extended bank.
Note:
I/O Locations 70h and 71h are used for data movement to and from the standard bank.
Locations 72h and 73h used for data movement to and from the extended bank. All of
these I/O locations also have alias I/O locations, as indicated in Table 126. Index
addresses above 127 are not valid.
Note:
Writes to 74h do not affect the NMI Enable bit of 70h
Table 126. I/O Registers Alias Locations
Register
Real-Time Clock (Standard RAM)
Index Register
Real-Time Clock (Standard RAM)
Target Register
Extended RAM Index Register
Extended RAM Target Register
Original I/O Location
70h
71h
72h
73h
Alias I/O Location
74h
75h
76h
77h
21.10.5
Indexed Registers
The RTC contains two sets of indexed registers, which are accessed using the two
separate Index and Target registers (70/71h or 72/73h).
Table 127. Indexed Registers
Start
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
End
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
7Fh
Name
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours
Hours Alarm
Day of Week
Day of Month
Month
Year
Register A
Register B
Register C
Register D
114 Bytes of User RAM
Intel® Quark SoC X1000
DS
880
October 2013
Document Number: 329676-001US
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