DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Bit
Default &
Range Access
Description
Timer Interrupt Type (IT): When cleared, interrupt is edge triggered. When set,
1
0b
RW
interrupt is level triggered and will be held active until it is cleared by writing 1 to
GIS.Tn. If another interrupt occurs before the interrupt is cleared, the interrupt remains
active.
0
0b
RO
Reserved (RSV1): Reserved.
21.9.3.12 Timer 1 Config and Capabilities Register - Upper 32 Bits (T1C_2)—
Offset 124h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
T1C_2: [0xFED00000] + 124h
Default: 00F00000h
31
28
24
20
16
12
8
4
0
00000000111100000000000000000000
Bit
Default &
Range Access
Description
31:0
00f00000h
RO
Interrupt Route
Capability (IRC):
Indicates
support
for
IRQ20,
21,
22,
23
21.9.3.13 Timer 1 Comparator Value Register (T1CV_1)—Offset 128h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
T1CV_1: [0xFED00000] + 128h
Default: FFFFFFFFh
31
28
24
20
16
12
8
4
0
11111111111111111111111111111111
Bit
Default &
Range Access
Description
31:0
FFFFFFFFh
RW
Comparator Value (CV): Reads return the current value of the 32 bits of the
comparator. Writes load the new value to the 32 bits of the comparator.
21.9.3.14 Timer 2 Config and Capabilities Register - Lower 32 Bits (T2C_1)—
Offset 140h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
T2C_1: [0xFED00000] + 140h
Default: 00000000h
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
875
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