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DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH
Intel
Intel 
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:16
0b
RO
Reserved (RSV3): Reserved.
15
0b
RO
FSB Interrupt Delivery (FID): Not Supported.
14
0b
RO
FSB Enable (FE): Not supported, since FID is not supported.
Interrupt Route (IR): Indicates the routing for the interrupt to the IOxAPIC. If the
13:9
0b
RW
value is not supported by this particular timer, the value read back will not match what
is written. If GC.LRE is set, then Timers 0 and 1 have a fixed routing, and this field has
no effect.
8
0b
RO
Timer 32-bit Mode (T32M): Not applicable since Timer 2 is a 32-bit timer.
7
0b
RO
Reserved (RSV2): Reserved.
6
0b
WO
Timer Value Set (TVS): This bit will return 0 when read. Writes will only have an effect
for Timer 0 if it is set to periodic mode.
5
0b
RO
Timer Size (TS): 1 = 64-bits, 0 = 32-bits. Set for timer 9. Cleared for timers 1 and 2
4
0b
RO
Periodic Interrupt Capable (PIC): When set, hardware supports a periodic mode for
this timer's interrupt.
3
0b
RO
Timer Type (TYP): If PIC is set, this bit is read/write, and can be used to enable the
timer to generate a periodic interrupt.
2
0b
RW
Interrupt Enable (IE): When set, enables the timer to cause an interrupt when it
times out. When cleared, the timer count and generates status bits, but will not cause
an interrupt.
Timer Interrupt Type (IT): When cleared, interrupt is edge triggered. When set,
1
0b
RW
interrupt is level triggered and will be held active until it is cleared by writing 1 to
GIS.Tn. If another interrupt occurs before the interrupt is cleared, the interrupt remains
active.
0
0b
RO
Reserved (RSV1): Reserved.
21.9.3.15 Timer 2 Config and Capabilities Register - Upper 32 Bits (T2C_2)—
Offset 144h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
T2C_2: [0xFED00000] + 144h
Default: 00F00800h
31
28
24
20
16
12
8
4
0
00000000111100000000100000000000
Intel® Quark SoC X1000
DS
876
October 2013
Document Number: 329676-001US

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