DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

21.9.3.8

Timer 0 Config and Capabilities Register - Upper 32 Bits (T0C_2)—

Offset 104h

Reads to this register return the current value of the comparator. The default value for

each timer is all 1's for the bits that are implemented. Timer 0 is 64-bits wide. Timers 1

and 2 are 32-bits wide.

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

T0C_2: [0xFED00000] + 104h

Default: 00F00000h

31

28

24

20

16

12

8

4

0

00000000111100000000000000000000

Bit

Default &

Range Access

Description

31:0

00f00000h

RO

Interrupt Route

Capability (IRC):

Indicates

support

for

IRQ20,

21,

22,

23

21.9.3.9

Timer 0 Comparator Value Register - Lower 32 Bits (T0CV_1)—Offset

108h

Reads to this register return the current value of the comparator. The default value for

each timer is all 1's for the bits that are implemented. Timer 0 is 64-bits wide. Timers 1

and 2 are 32-bits wide.

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

T0CV_1: [0xFED00000] + 108h

Default: FFFFFFFFh

31

28

24

20

16

12

8

4

0

11111111111111111111111111111111

Bit

Default &

Range Access

Description

31:0

FFFFFFFFh

RW

Comparator Value (CV): Reads return the current value of the lower 32 bits of the

comparator. Writes load the new value to the lower 32 bits of the comparator.

21.9.3.10 Timer 0 Comparator Value Register - Upper 32 Bits (T0CV_2)—Offset

10Ch

Reads to this register return the current value of the comparator. The default value for

each timer is all 1's for the bits that are implemented. Timer 0 is 64-bits wide. Timers 1

and 2 are 32-bits wide.

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

T0CV_2: [0xFED00000] + 10Ch

Default: FFFFFFFFh

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

873

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