DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
| |||
Intel® Quark SoC X1000—Legacy Bridge
31
28
24
20
16
12
8
4
0
11111111111111111111111111111111
Bit
Default &
Range Access
Description
31:0
FFFFFFFFh
RW
Comparator Value (CV): Reads return the current value of the upper 32 bits of the
comparator. Writes load the new value to the upper 32 bits of the comparator.
21.9.3.11 Timer 1 Config and Capabilities Register - Lower 32 Bits (T1C_1)—
Offset 120h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
T1C_1: [0xFED00000] + 120h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:16
0b
RO
Reserved (RSV3): Reserved.
15
0b
RO
FSB Interrupt Delivery (FID): Not Supported.
14
0b
RO
FSB Enable (FE): Not supported, since FID is not supported.
Interrupt Route (IR): Indicates the routing for the interrupt to the IOxAPIC. If the
13:9
0b
RW
value is not supported by this particular timer, the value read back will not match what
is written. If GC.LRE is set, then Timers 0 and 1 have a fixed routing, and this field has
no effect.
8
0b
RO
Timer 32-bit Mode (T32M): Not applicable since Timer 1 is a 32-bit timer.
7
0b
RO
Reserved (RSV2): Reserved.
6
0b
WO
Timer Value Set (TVS): This bit will return 0 when read. Writes will only have an effect
for Timer 0 if it is set to periodic mode.
5
0b
RO
Timer Size (TS): 1 = 64-bits, 0 = 32-bits. Set for timer 9. Cleared for timers 1 and 2
4
0b
RO
Periodic Interrupt Capable (PIC): When set, hardware supports a periodic mode for
this timer's interrupt. This bit is set for timer 0, and cleared for timers 1 and 2
3
0b
RO
Timer Type (TYP): If PIC is set, this bit is read/write, and can be used to enable the
timer to generate a periodic interrupt. This bit is RW for timer 0, and RO for timers 1
and 2.
2
0b
RW
Interrupt Enable (IE): When set, enables the timer to cause an interrupt when it
times out. When cleared, the timer count and generates status bits, but will not cause
an interrupt.
Intel® Quark SoC X1000
DS
874
October 2013
Document Number: 329676-001US
Share Link: 